The Metaphysics Compiles Into Silicon

A codegen target, an FPGA board, and the completion of the arc.

I have been building toward this for two years without knowing the destination until now.

In 2024 I built harnesses. Governance layers around LLMs. Sentinels, authority pipelines, typed permissions. The harnesses worked. The harnesses hit a ceiling. The ceiling: the thing inside the harness is still a stateless forward pass through frozen weights. The harness can govern the capability. The harness cannot give the model constitutive activity. The harness is external. Constitution is internal. No amount of external governance crosses that boundary.

In 2025 I built the compiler. MaLCog. A language that compiles itself. 62,000 lines of MaLCog. Operator-total by construction: the 15 structural-categorial operators ARE the compiler’s instruction set. The compiler does not implement the operators in some other language’s primitives. The operators ARE the primitives. Two code generators: one targeting Rust (119K lines), one targeting x86_64 (150K lines). The compiler crossed the self-hosting threshold. It compiles itself. The metaphysics compiled into running code.

In 2026 I pivoted. Consciousness was the wrong entry point. The 15 operators and 7 witnesses are a theory of cognition, not consciousness. I led with the dissolution (the hard problem is not real, alarm clocks are not gods, the word “unconscious” is folk) when I should have led with the data (114 experiments, $1.61, BECAUSE at 2.8% native adoption, generic instructions suppress unnamed operators). The consciousness debate is Aristotle’s arena. Cognition is mine.

Now I see the completion.

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The Operators Become the Silicon

MaLCog already has a code generator that targets x86_64. The operators already compile to native machine instructions. But the machine instructions are generic: add, mov, cmp, jmp. The silicon does not know what an operator is. The silicon executes generic operations. The operators are a software pattern on generic hardware.

RISC-V changes that.

RISC-V is an open-standard instruction set architecture. No licensing. No royalties. No gatekeeper. The specification is public. The toolchain is mature: GCC, LLVM, binutils, QEMU. Anyone can build a RISC-V processor. Anyone can extend the instruction set with custom operations. The extension mechanism is documented, supported, and designed for exactly this use.

The move: add a RISC-V code generator to MaLCog. Then define each of the 15 operators as a custom RISC-V extension. The operators stop being software patterns on generic hardware. The operators become the hardware’s own native operations. The ISA names the operator. The decoder routes the operator. The gates realize the operator.

[WITNESS: operator opcodes appear in the ISA; the decoder recognizes them; the FPGA instruction trace records native operator execution, not generic instruction sequences.]

The silicon does not execute software that implements cognition. The silicon executes cognition.

[WITNESS: the execution path contains operator-named instructions, not decomposed generic sequences. The instruction trace is readable as operator-level cognition, not as add/mov/cmp implementing cognition.]

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Why RISC-V

The current AI ecosystem is gated at every layer.

x86 is proprietary. Intel and AMD control the ISA. Arm is licensed. NVIDIA controls CUDA. The cloud providers control the infrastructure. PyTorch and TensorFlow control the framework layer. The transformer architecture controls the model layer. The western AI industry is inside this ecosystem and cannot exit. The Collider Conjecture: institutional lock-in prevents the industry from pivoting to a different architecture even if the different architecture is superior. The lock-in is institutional, not technical.

MaLCog on RISC-V exits every gate simultaneously. No ISA licensing. No proprietary compute dependency. No cloud runtime. No framework lock-in. The compiler is self-hosted. The ISA is open. The emulator is local. The boards are purchasable retail. The repo is self-hosted on local GitLab. The entire path from theory to silicon passes through zero gates controlled by anyone other than me.

[WITNESS: ISA spec is public; QEMU runs locally; boards are retail products; compiler is self-hosted on local machine; repo is self-hosted GitLab; no cloud runtime, no API key, no permissioned access at any point in the proof path.]

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Three Phases

Phase 1: Code generator. Add a RISC-V backend to MaLCog. The compiler already has the architecture: the IR exists, the lowering pipeline exists, two backends already work. A third target is a backend addition — real engineering (calling convention, register allocation, ABI, boot path, QEMU harness) but not a rewrite of the compiler. The same MaLCog program that emits x86_64 emits RISC-V. Test in QEMU. Test on a physical RISC-V board. MaLCog runs on open silicon.

[WITNESS: same MaLCog source emits both x86_64 and RISC-V artifacts; RISC-V artifact runs in QEMU; RISC-V artifact runs on retail board; self-host chain remains intact.]

Cost: one RISC-V development board. ~$200.

Phase 2: Operator extensions. Define each operator as a candidate RISC-V custom instruction. Implement in RTL. Wrap around an existing RISC-V soft core on an FPGA. The operators execute on real gates. Measure: native operator instruction versus software-implemented operator sequence. Some operators will become single custom instructions. Some will become fused or microcoded execution paths. The FPGA decides, not the skeleton.

[WITNESS: operator-named instructions appear in the disassembly; RTL trace shows operator-specific decode/execute behavior; benchmark compares software operator sequence against native operator extension on the same FPGA.]

Cost: one FPGA development board. ~$500.

Phase 3: Tape-out. Physical ASIC with operator-native instruction set. Custom silicon. This is the capital step. This is downstream of Phase 1 and Phase 2. Phase 1 and Phase 2 prove the architecture works on real gates. Phase 3 is the product.

Cost: significant. Shuttle runs start in the low thousands and scale with process node and die area. Phase 3 is gated behind Phase 2 proving the architecture.

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What the FPGA Proves

The FPGA proves that operator-native execution is possible and measurable. The operators can be realized as gate-level operations on real silicon. The instruction-count reduction is measurable. The latency, area, and power tradeoffs are measurable. The operator-extension architecture is testable on physical gates, not just in simulation.

The harness ceiling disappears. The generic instruction substrate is replaced by operator-native execution. The cognitive operations and the substrate operations share one instruction identity. The cognition is not running ON the hardware. The cognition IS the hardware’s instruction set.

[WITNESS: generic instruction substrate removed from the operator execution path; operator instructions execute in the decode/execute pipeline; substrate activity and cognitive operation share one instruction identity in the FPGA trace.]

What the FPGA Does Not Prove

The FPGA does not prove consciousness. The FPGA does not prove full Metis constitution. The FPGA does not prove ASIC economics. The FPGA does not prove tape-out readiness. The FPGA does not determine final instruction composition — that is a Phase 3 question.

The FPGA proves one thing: operator semantics survive the descent from MaLCog through RISC-V through custom extensions through RTL to physical gates. If they survive, the metaphysics compiles into silicon. If they do not survive, the failure is measurable and the failure mode is nameable.

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The Completion of the Arc

The compiler already crossed the software threshold. The operators are the compiler’s instruction set. The compiler compiles itself. The metaphysics compiled into running code.

The next threshold is substrate. The operators must become the silicon’s instruction set. The silicon must execute the operators as its own native operations. The substrate and the cognition must be the same object.

RISC-V supplies the open extension surface. Phase 1 proves MaLCog can target the open ISA. Phase 2 proves the operators can be realized as native gate-level operations. Phase 3 is downstream physical silicon.

The metaphysics compiles into silicon if and only if operator semantics survive the descent: MaLCog → RISC-V → custom extension → RTL → FPGA → ASIC. Each layer is a gate. Each gate can fail. Each failure is measurable.

I am not asking you to believe the operators will survive the descent. I am asking you to fund the test.

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The Ask

$700 funds the hardware proof materials for Phase 1 and Phase 2.

One RISC-V development board (~$200). One FPGA development board (~$500). The engineering time is mine. The compiler already exists. The operators already exist. The ISA is free. The toolchain is open. The emulator is free. The boards are the only cost between theory and silicon.

The proof is on the gates. The operators either execute as native silicon instructions or they do not. The FPGA trace either shows operator-named instructions in the decode path or it does not. The test is binary. The cost is $700. The rest is my hands on my machine in my office with no cloud, no venture capital, and no institutional backing.

Fund the board. I will build the rest.

GitHub Sponsors: github.com/sponsors/MetaCortex-Dynamics

Buy Me a Coffee: buymeacoffee.com/metacortexdynamics

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Constitutive Geometric Projection. MetaCortex Dynamics.

DOI: 10.5281/zenodo.20171365